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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002-2005, zarlink semiconductor inc. all rights reserved. not recommended for new designs. use the zl38065, 32 channel vec with enhanced algorithm. features ? independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination ? independent power down mode for each group of 2 channels for power management ? itu-t g.165 and g.168 compliant ? field proven, high quality performance ? compatible to st-bus and gci interface at 2 mbps serial pcm ? pcm coding, /a-law itu-t g.711 or sign magnitude ? per channel fax/modem g.164 2100 hz or g.165 2100 hz phase reversal tone disable ? per channel echo canceller parameters control ? transparent data transfer and mute ? fast reconvergence on echo path changes ? non-linear processor with high quality subjective performance ? protection against narrow band signal divergence ? offset nulling of all pcm channels ? 10 mhz or 20 mhz master clock operation ? 3.3 v pads and 1.8 v logic core operation with 5 v tolerant inputs ? no external memory required ? non-multiplexed microprocessor interface ? ieee-1149.1 (jtag) test access port ?applications ? voice over ip network gateways ? voice over atm, frame relay ? t1/e1/j1 multichannel echo cancellation ? wireless base stations ? echo canceller pools ? dcme, satellite and multiplexer systems march 2005 ordering information MT93L00AB 100-pin lqfp mt93l00av 208-ball lbga -40 c to +85 c mt93l00a multi-channel voice echo canceller data sheet figure 1 - functional block diagram reset rout ic0 sout ds cs r/w a10-a0 dta d7-d0 echo canceller pool v ss v dd1 (3.3 v) tdi tdo tck trst tms rin irq c4i f0i mclk ode sin fsel test port microprocessor interface timing unit serial to parallel parallel to serial pll group 0 eca/ecb group 4 eca/ecb group 8 eca/ecb group 12 eca/ecb group 1 eca/ecb group 5 eca/ecb group 9 eca/ecb group 13 eca/ecb group 2 eca/ecb group 6 eca/ecb group 10 eca/ecb group 14 eca/ecb group 3 eca/ecb group 7 eca/ecb group 11 eca/ecb group 15 eca/ecb note: refer to figure 4 for echo canceller block diagram v dd2 (1.8 v)
mt93l00a data sheet 2 zarlink semiconductor inc. description the mt93l00 voice echo canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to itu-t g.168 requirements. the mt93l00 architecture contains 16 groups of two echo cancellers (eca and ecb) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. this pr ovides 32 channels of 64 milliseconds to 16 channels of 128 milliseconds echo cancellation or any combination of the two confi gurations. the mt9 3l00 supports itu-t g.165 and g.164 tone disable requirements. figure 2 - 100 pin lqfp 31 30 50 17 11 9 725 23 21 19 3 5 13 15 1 d7 d6 d5 d4 d3 d2 d1 d0 cs ds vss nc r/w dta 2 4 6 8 10121416182022 24 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 29 28 27 26 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 100 77 99 76 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 a1 a2 a3 a4 a5 a0 vdd1 vdd2 nc vss a6 a7 a8 a9 a10 vss vdd2 vdd1 vss vss pllvss2 nc ode sout rout sin nc nc vss c4ib foib rin vdd2 vdd2 mclk fsel pllvss1 pllvdd vdd1 tms tdi tdo tck vss trstb resetb irqb MT93L00AB nc (100 pin lqfp) v dd1 = 3.3 v v dd2 = 1.8 v nc vdd1 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 ic0 nc
mt93l00a data sheet 3 zarlink semiconductor inc. figure 3 - 208 ball lbga b c d e f g h j k l m n 12345678910111213 1 - a1 corner is identifi ed by metallized markings. a 14 15 16 p r t 1 v dd2 c4i f0i rin sin rout ode a1 sout mclk fsel tms tdi tck reset irq ds cs r/w dta d0 d1 d2 d4 d5 d6 d7 a10 a9 a8 a7 a6 a5 a4 a3 a2 mt93l00av v dd1 ico pllvss pllvdd ico ico ico ico ico ico ico ico ico ico ico ico ico ico v dd1 v ss nc nc tdo trst a0 d3 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd1 v dd2 v dd2 v dd2 v dd2 v dd2 v dd2 v dd2 v ss v ss v ss v ss v ss v dd1 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss
mt93l00a data sheet 4 zarlink semiconductor inc. pin description pin # pin name description 208-ball lbga 100 pin lqfp a1,a3,a7,a11,a13,a15, a16,b2,b6,b8,b12, b14,b15,b16,c3,c5,c7, c9,c11,c12,c13,c14, c16, d4,d8,d10,d12,d13,e3, e4,e14,f13,g3,g4,g7,g8, g9,g10,h7,h8,h9, h10,h13,h14,j7,j8,j9, j10,k7,k8,k9,k10,k13, k14,l3,l4,m13,m14,m15, n3,n4,n5,n7,n9,n11,n13, p2,p3,p5,p7,p9.p11,p13, p14,r2,r14,r15,r16,t1, t3,t7,t10, t14,t16 5, 18, 32, 42, 56, 69, 81, 98 v ss ground. a5,a9,b4,b10,c4,c8,c10, d3,d5,d7,d9,d11,d14,e1 3, f3,f4,f14,h3,h4,j13,j14, l13,l14,m3,m4,n6,n8, n10,n14,n15,p4,p6,p8, p10,p15,r4,r6,r8,r10, r12,t5,t12 27, 48, 77, 100 v dd1 positive power supply. nominally 3.3 v c6,d6,j3,j4,n12,p12, g13,g14 14, 37, 64, 91 v dd2 these pins should be wired to vdd2= 1.8 v. e15,f15,a12,a10,a6,a2, b1,b3,c1,c2,d2,e2,j2,k2, r1 7,41,43,65,6 6,67,68,70, 71,72,86,87, 88,93,94 ic0 internal connection. these pins must be connected to v ss for normal operation. a14,c15,d1,d15,e1,f1, g1, g15,h1,h15,j1,j15,k1, k15,l1,l15,f2,l2 24,25,26,44, 45,46,47,49, 51,52,53,54, 55,73,74,75, 76,78,79,80, 82,83,84,85, 89,99 nc no connection. these pins must be left open for normal operation. r9 9 irq interrupt request (open drain output). this output goes low when an interrupt occurs in any channel. irq returns high when all the interrupts have been read from the interrupt fifo register. a pull-up resistor (1 k typical) is required at this output. r11 10 ds data strobe (input) . this active low input works in conjunction with cs to enable the read and write operations. r13 11 cs chip select (input). this active low input is used by a microprocessor to activate the microprocessor port. r5 12 r/w read/write (input) . this input controls the direction of the data bus lines (d7-d0) during a microprocessor access.
mt93l00a data sheet 5 zarlink semiconductor inc. r7 13 dta data transfer acknowledgment (open drain output) . this active low output indicates that a data bus transfer is completed. a pull-up resistor (1 k typical) is required at this output. t2,t4,t6,t8,t9,t11, t13,t15 15,16,17, 19,20,21, 22,23 d0 - d3, d4 - d7 data bus d0 - d7 (bidirectional) . these pins form the 8-bit bidirectional data bus of the microprocessor port. p16,n16,m16,l16,k16, j16,h16,g16,f16,e16, d16 28,29,30,31, 33,34,35,36, 38,39,40 a0 - a10 address a0 to a10 (input) . these inputs provide the a10 - a0 address lines to the internal registers. b13 57 ode output drive enable (input). this input pin is logically and?d with the ode bit-6 of the main control register. when both ode bit and ode input pin are high, the rout and sout st-bus outputs are enabled. when the ode bit is low or the ode input pin is low, the rout and sout st-bus outputs are high impedance. a8 58 sout send pcm signal output (output) . port 1 tdm data output streams. sout pin outputs serial tdm data streams at 2.048 mbps with 32 channels per stream. b9 59 rout receive pcm signal output (output) . port 2 tdm data output streams. rout pin outputs se rial tdm data streams at 2.048 mbps with 32 channels per stream. b11 60 sin send pcm signal input (input). port 2 tdm data input streams. sin pin receives serial tdm data streams at 2.048 mbps with 32 channels per stream. b7 61 rin receive pcm signal input (input). port 1 tdm data input streams. rin pin receives serial tdm data streams at 2.048 mbps with 32 channels per stream. b5 62 f0i frame pulse (input). this input accepts and automatically identifies frame synchronization signals formatted according to st-bus or gci interface specifications. a4 63 c4i serial clock (input). 4.096 mhz serial clock for shifting data in/out on the serial stre ams (rin, sin, rout, sout). g2 90 mclk master clock (input). nominal 10 mhz or 20 mhz master clock input. may be connected to an asynchronous (relative to frame signal) clock source. h2 92 fsel frequency select (input). this input selects the master clock frequency operation. when fsel pin is low, nominal 19.2 mhz master clock input must be app lied. when fsel pin is high, nominal 9.6 mhz master clock input must be applied. pin description (continued) pin # pin name description 208-ball lbga 100 pin lqfp
mt93l00a data sheet 6 zarlink semiconductor inc. device overview the mt93l00 architecture contains 32 echo cancellers divided into 16 groups. each group has two echo cancellers, echo canceller a and echo canceller b. each group can be configured in normal, extended delay or back-to-back configurations. in normal configuration , a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. in extended delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (a & b). in back-to- back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, provid ing full-duplex 64 ms echo cancellation. each echo canceller contains the following main elements (see figure 4). ? adaptive filter for estimating the echo channel ? subtractor for cancelling the echo ? double-talk detector for disabling the filt er adaptation during periods of double-talk ? path change detector for fast reconvergence on major echo path changes ? instability detector to combat oscillation in very low erl environments ? non-linear processor for suppression of residual echo k3 95,97 pllvss1 pllvss2 pll ground. must be connected to v ss. k4 96 pllv dd pll power supply. must be connected to v dd2. m2 1 tms test mode select (3.3 v input). jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull-up when not driven. m1 2 tdi test serial data in (3.3 v input). jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up when not driven. n1 3 tdo test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. p1 4 tck test clock (3.3 v input). provides the clock to the jtag test logic. n2 6 trst test reset (3.3 v input). asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up or held low, to ensure that the mt93l00 is in the normal functional mode. this pin is pulled by an internal pull-down when not driven. r3 8 reset device reset (schmitt trigger input). an active low resets the device and puts the mt93l00 into a low-power stand-by mode. when the reset pin is returned to logic high and a clock is applied to the mclk pin, the device will automatically execute initialization routines, which preset all the control and status registers to their default power-up values. pin description (continued) pin # pin name description 208-ball lbga 100 pin lqfp
mt93l00a data sheet 7 zarlink semiconductor inc. ? disable tone detectors for detecting valid disable tones at send and receive path inputs ? narrow-band detector for preventing adaptive filter divergence from narrow-band signals ? offset null filters for removing the dc component in pcm channels ? 12 db attenuator for signal attenuation ? parallel controller interface compatib le with motorola microcontrollers ? pcm encoder/decoder compatible with /a-law itu-t g.711 or sign-magnitude coding each echo canceller in the mt93l00 has four functional states: mute , bypass , disable adaptation and enable adaptation . these are explained in the section entitled echo canceller functional states. figure 4 - echo canceller functional block diagram adaptive filter the adaptive filter adapts to the echo path and generates an es timate of the echo signal. this echo estimate is then subtracted from sin. for each group of echo cancellers, the adaptive filter is a 1024 tap fir adaptive filter which is divided into two sections. each section contains 512 taps providing 64 ms of echo estimation. in normal configuration , the first section is dedicated to channel a and the second section to channel b. in extended delay configuration , both sections are cascaded to provide 12 8 ms of echo estimation in channel a. in back-to back configuration , the first section is used in the receive directi on and the second section is used in the transmit direction for the same channel. linear/ /a-law + non-linear processor offset null /a-law/ linear linear/ /a-law microprocessor interface double-talk detector disable tone detector adaptive filter control narrow-band detector /a-law/ linear offset null echo canceller (n), where 0 n 31 sout rin sin rout - programmable bypass disable tone detector (channel n) (channel n) (channel n) (channel n) st-bus st-bus port2 port1 12 db attenuator muter mutes instability detector path change detector
mt93l00a data sheet 8 zarlink semiconductor inc. double-talk detector double-talk is defined as those period s of time when signal energy is pres ent in both directions simultaneously. when this happens, it is necessary to disable the filt er adaptation to prevent dive rgence of the adaptive filter coefficients. note that when double-ta lk is detected, the adaptation proces s is halted but the echo canceller continues to cancel echo using t he previous converged echo profile. a double-talk condition exists whenever the relative signal levels of rin (lrin) and si n (lsin) meet the following condition: lsin > lrin + 20log 10 (dtdt) where dtdt is the double-talk detection threshold. lsin and lrin are signal levels expressed in dbm0. a different method is used when it is uncertain whethe r sin consists of a low level double-talk signal or an echo return. during these periods, the adaptation proc ess is slowed down but it is not halted. in g.168 standard, the echo return loss is expected to be at least 6 db. this implies that the double-talk detector threshold (dtdt) should be set to 0.5 (-6 db). however, in order to get additional guardband, the dtdt is set internally to 0.5625 (-5 db). in some applications the return loss can be higher or lower than 6 db. the mt93l00 allows the user to change the detection threshold to suit each application?s need. this threshold can be set by writing the desired threshold value into the dtdt register. the dtdt register is 16 bits wide. th e register value in hexadecimal can be calculated with the following equation: dtdt (hex) = hex(dtdt (dec) * 32768) where 0 < dtdt (dec) < 1 example: for dtdt = 0.5625 (-5 db), the hexadecimal value becomes hex( 0.5625 * 32768 ) = 4800h path change detector integrated into the mt93l00a is a path change detector. this permits fast reconvergence when a major change occurs in the echo channel. subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. the path change detector is activated by setting the pathde t bit in control register a3 /b3 to "1". an optional path clearing feature can be enabled by setting the pathclr bit in control register a3/b3 to "1". with path clearing turned on, the existing echo channel estimate will also be cleare d (i.e. the adaptive filter will be filled with zeroes) upon detection of a major path change.
mt93l00a data sheet 9 zarlink semiconductor inc. non-linear processor (nlp) after echo cancellation, there is alwa ys a small amount of residual echo which may still be audible. the mt93l00 uses an nlp to remove residual echo signals which hav e a level lower than the adaptive suppression threshold (tsup in g.168). this threshold depends upon the level of the rin (lrin) reference signal as well as the programmed value of the non- linear processor threshold register (nlp thr). tsup can be calculated by the following equation: tsup = lrin + 20log 10 (nlpthr) where nlpthr is the non-linear processor threshold r egister value and lrin is the relative power level expressed in dbm0. when the level of residual error signal falls below tsup, the nlp is activated further attenuating the residual signal by an additional 36 db. to prevent a perceived decrease in background noise due to the activation of the nlp, a spectrally-shaped comfort noise , equivalent in power level to the backgr ound noise, is injected. this keeps the perceived noise level constant. cons equently, the user does not hear the ac tivation and de-activation of the nlp. the nlp processor can be disabled by setting the nlpdis bit to ?1? in control register 2. the nlpthr register is 16 bits wide. the register valu e in hexadecimal can be calculated with the following equation: nlpthr (hex) = hex(nlpthr (dec) * 32768) where 0 < nlpthr (dec) < 1 the comfort noise injector can be disabled by setting the in jdis bit to ?1? in control register a1/b1. it should be noted that the nlpthr is valid and the comfort noise injection is active only when the nlp is enabled. if the comfort noise injector is unable to correctly ma tch the level of the background noise (because of peculiar spectral characteristics, for exampl e), the injected level can be fine-tuned using the noise scaling register. a neutral value of 80 (hex) will prevent any scaling . values less than 80 (hex) will reduce the noise level, values greater than 80 (hex) will increase the noise level. the scaling is done linearly. example: to decrease the comfort noise level by 3 db, the register value would be 10 ^ (-3 / 20) ? 128 = 0.71 ? 128 = 91 (dec) = 5b (hex) the default factory setting for the noise scaling register should be adequate for most operating environments. it is unlikely that it will need to be changed. it has also been set to a value which will ensure g.168 compliance. disable tone detector g.165 recommendation defines the di sable tone as having the following characteristics: 2100 hz ( 21 hz) sine wave, a power level between -6 to -31 dbm0, and a phase reversal of 180 degrees ( 25 degrees) every 450 ms ( 25 ms). if the disable tone is present for a minimum of one second with at least one phase reversal, the tone detector will trigger.
mt93l00a data sheet 10 zarlink semiconductor inc. g.164 recommendation defines the disable tone as a 2100 hz ( 21 hz) sine wave with a power level between 0 to -31 dbm0. if the disable tone is present for a minimum of 400 milliseconds, with or wit hout phase reversal, the tone detector will trigger. the mt93l00 has two tone detectors per c hannels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both rin and sin. upon detection of a disabl e tone, td bit of the status register will indicate logic high and an interrupt is generated (i.e. irq pin low). refer to figure 5 and to the interrupts section. figure 5 - disable tone detection once a tone detector has been triggered, there is no long er a need for a valid disable tone (g.164 or g.165) to maintain tone detector status (i.e. td bi t high). the tone detector status will only release (i.e. td bit low) if the signals rin and sin fall below -30 dbm0, in the frequency range of 390 hz to 700 hz, and below -34 dbm0, in the frequency range of 700 hz to 3400 hz, for at least 400 ms . whenever a tone detector releases, an interrupt is generated (i.e. irq pin low). the selection between g.165 and g.164 tone disable is cont rolled by the phdis bit in control register 2 on a per channel basis. when the phdis bit is set to 1, g.164 tone disable requirements are selected. in response to a valid disable tone, the echo canceller must be switched from the enable adaptation state to the bypass state. this can be done in two ways, automatica lly or externally. in automa tic mode, the tone detectors internally control the switching betw een enable adaptation and bypass states . the automatic mode is activated by setting the autotd bit in control register 2 to high. in external mode, an exte rnal controller is needed to service the interrupts and poll the td bits in the status registers. following the detection of a di sable tone (td bit high) on a given channel, the external controller must switch the echo canceller from enable adaptation to bypass state. instability detector in systems with very low echo channel return loss (erl ), there may be enough feedback in the loop to cause stability problems in the adaptive filter. this instability can result in variabl e pitched ringing or oscillation. should this ringing occur, the instability detector wi ll activate and suppres s the oscillations. the instability detector is activa ted by setting the ringclr bit in control register a3/b3 to "1". narrow band signal detector (nbsd) single or dual frequency tones (i.e. dtmf tones) present in the receive input (rin) of the echo canceller for a prolonged period of time may cause t he adaptive filter to diverge. the na rrow band signal detector (nbsd) is designed to prevent this by detecting single or dual to nes of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, adaptation is halted but the echo canc eller continues to cancel echo. the nbsd can be disabled by setting the nbdis bit to ?1? in control register 2. td bit rin sin echo canceller a tone detector tone detector status reg eca td bit rin sin echo canceller b tone detector tone detector status reg ecb
mt93l00a data sheet 11 zarlink semiconductor inc. offset null filter adaptive filters in general do not operate properly when a dc offset is present at any inputs. to remove the dc component, the mt93l00 incorporates offset null filters in both rin and sin inputs. the offset null filters can be disabled by setti ng the hpfdis bit to ?1? in control register 2. itu-t g.168 compliance the mt93l00 has been certified g.168 compliant in all 64 ms cancellation modes (i.e. normal and back-to-back configurations) by in-house testing with the dspg ect-1 echo canceller tester. it should be noted that g.168 compliance is not claimed for the 128 ms extended delay mode, although subjectively no difference can be noticed. device configuration the mt93l00 architecture contains 32 echo cancellers divi ded into 16 groups. each group has two echo cancellers which can be individually controlled (echo canceller a and b). they can be set in three distinct configurations: normal, back-to-back, and extended delay . see figure 6. normal configuration in normal configuration, the two echo cancellers (echo canceller a and b) are positioned in parallel, as shown in figure 6a, providing 64 milliseconds of echo cancellation in two channels simultaneously. back-to-back configuration in back-to-back configuratio n, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing fu ll-duplex 64 ms echo cancellation. see figure 6c. this configuration uses only one timeslot on port1 and port 2 and the second timeslot nor mally associated with ecb contains undefined data. back-to-back configuration allows a no-glue interf ace for applications where bidirectional echo cancellation is required. back-to-back configuration is selected by writing ?1? into the bbm bit of both control register a1 and control register b1 of a given group of echo cancellers. table 2 s hows the 16 groups of 2 cancellers that can be configured into back-to-back. examples of back-to-back configuration include positi oning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. extended delay configuration in this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. see figure 6b. this conf iguration uses only one timesl ot on port1 and port2 and the second timeslot normally associated with ecb contains undefined data. extended delay configuration is selected by writing ?1? into the extdl bit in echo canceller a, control register a1. for a given group, only echo canceller a, control register a1, has the extdl bit. control register b1, bit-0 must always be set to zero. table 2 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity.
mt93l00a data sheet 12 zarlink semiconductor inc. echo canceller functional states each echo canceller has four functional states: mute, bypass, disable adaptation and enable adaptation . mute in normal and in extended delay confi gurations, writing a ?1? into the muter bit replaces rin with quiet code which is applied to both the adaptive filter and rout. writing a ?1? into the mutes bit replaces the sout pcm data with quiet code. in back-to-back configuration, writing a ?1? into the muter bit of echo canceller a, control register 2, causes quiet code to be transmitted on rout. writing a ?1? into the mutes bit of echo canceller a, control register 2, causes quiet code to be transmitted on sout. in extended delay and in back -to -back configurations, muter and mutes bits of echo canceller b must always be ?0?. refer to figure 4 and to control register 2 for bit description. bypass the bypass state directly transfers pcm codes from rin to rout and from sin to sout. when bypass state is selected, the adaptive filter coefficients are reset to zero. bypass state must be selected for at least one frame (125 s) in order to properly clear the filter. figure 6 - device configuration linear 16 bits 2?s complement sign/ magnitude -law a-law ccitt (g.711) -law a-law +zero (quiet code) 0000h 80h ffh d5h table 1 - quiet pcm code assignment rin rout sout sin echo path a optional -12db pad echo path b + - channel a channel a + - channel b channel b e.c.a e.c.b a) normal configuration (64 ms) adaptive filter (64 ms) adaptive filter (64 ms) optional -12db pad port1 port2 + - channel a channel a e.c.a sin sout rout rin b) extended delay configuration (128 ms) echo path a adaptive filter (128 ms) optional -12db pad port1 port2 + e.c.a sin sout rout rin c) back-to-back configuration (64 ms) - e.c.b + - echo echo path path adaptive filter (64 ms) optional -12db pad adaptive filter (64 ms) optional -12db pad port1 port2
mt93l00a data sheet 13 zarlink semiconductor inc. disable adaptation when the disable adaptation state is selected, the adaptive fi lter coefficients are frozen at their current value. the adaptation process is halted, however, the echo canceller continues to cancel echo. enable adaptation in enable adaptation state, the adaptive filter coefficients are continually u pdated. this allows the echo canceller to model the echo return path characteristics in orde r to cancel echo. this is the normal operating state. the echo canceller functions are selected in control regist er a1/b1 and control register 2 through four control bits: mutes, muter, bypass and adaptdis. refe r to the registers description for details. figure 7 - st-bus and gci interface channel assignment for 2 mbps data streams mt93l00 throughput delay the throughput delay of the mt93l00 varies according to t he device configuration. for all device configurations, rin to rout has a delay of two frames and sin to sout has a delay of three frames. in bypass state, the rin to rout and sin to sout paths have a delay of two frames. serial pcm i/o channels there are two sets of tdm i/o streams, each with channels numbered from 0 to 31. one set of input streams is for receive (rin) channels, and the other set of input stream s is for send (sin) channels. likewise, one set of output streams is for rout pcm channels, and the other set is for sout channels. see figure 7 for channel allocation. the arrangement and connection of pcm channels to each ec ho canceller is a two port i/o configuration for each set of pcm send and receive channels, as illustrated in figure 4. serial data interface timing the mt93l00 provides st-bus and gci interface ti ming. the serial interf ace clock frequency, c4i , is 4.096 mhz. the input and output data rate of the st-bus and gci bus is 2.048 mbps. the 8 khz input frame pulse can be in either st-bus or gci format. the mt93l00 automatically detects the presence of an input frame pulse and identifies it as either st-bus or gci. in st-bus format , every second falling edge of the c4i clock marks a bit boundary, and the data is clocked in on the rising edge of c4i , three quarters of the way into the bit cell (see figure 11). in gci format, every second rising edge of the c4i clock marks the bit boundary, and data is clocked in on the second falling edge of c4i , half the way into the bit cell (see figure 12). f0i rin/sin rout/sout channel 31 channel 0 125 sec channel 1 channel 30 st-bus f0i gci interface note: refer to figures 11 and 12 for timing details
mt93l00a data sheet 14 zarlink semiconductor inc. figure 8 - memory mapping of per ch annel control and status registers memory mapped control and status registers internal memory and registers are memory mapped into the address space of the host interface. the internal dual ported memory is mapped into segments on a ?per channe l? basis to monitor and control each individual echo canceller and associated pcm channels. for example, in normal configuration , echo canceller #5 makes use of echo canceller b from group 2. it occupies the internal address space from 0a0h to 0bfh and interfaces to pcm channel #5 on all serial pcm i/o streams. as illustrated in figure 8, the ?p er channel? registers prov ide independent control and status bits for each echo canceller. figure 9 shows the memory map of the cont rol/status register blocks for all echo cancellers. when extended delay or back-to-back configuration is selected, control re gister a1/b1 and control register 2 of the selected group of echo cancellers require spec ial care. refer to the regi ster description section. 00h control reg a1 01h decay step size reg 02h 03h base 04h 06h reserved flat delay reg control reg 2 status reg reserved 05h control reg a3 08h decay step number 07h control reg a4 09h rin peak detect reg 0ch sin peak detect reg 0eh error peak detect reg 10h reserved 12h dtdt reg 14h reserved 16h nlpthr 18h step size, mu 1ah reserved 1ch reserved 1eh addr + echo canceller a 20h control reg b1 21h decay step size reg 22h 23h 24h 26h reserved flat delay reg control reg 2 status reg reserved 25h control reg b3 28h decay step number 27h control reg b4 29h rin peak detect reg 2ch sin peak detect reg 2eh error peak detect reg 30h reserved 32h dtdt reg 34h reserved 36h nlpthr 38h step size, mu 3ah reserved 3ch reserved 3eh base addr + echo canceller b noise scaling 0ah injection rate 0bh noise scaling 2ah injection rate 2bh
mt93l00a data sheet 15 zarlink semiconductor inc. table 2 is a list of the channels used for the 16 grou ps of echo cancellers when they are configured as extended delay or back-to-back . normal configuration for a given group (group 0 to 15), 2 pcm i/o channels are used. for example, group 1 echo cancellers a and b, channels 2 and 3 are active. extended delay configuration for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries don?t care data. for example, group 2, echo canc eller a (channel 4) will be active and echo canceller b (channel 5) will carry don?t care data. back-to-back configuration for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries don?t care data. for example, group 5, echo canceller a (channel 10) will be active and echo canceller b (channel 11) will carry don?t care data. group channel group channel 0 0, 1 8 16, 17 1 2, 3 9 18, 19 2 4, 5 10 20, 21 3 6, 7 11 22, 23 4 8, 9 12 24, 25 5 10, 11 13 26, 27 6 12, 13 14 28, 29 7 14, 15 15 30, 31 table 2 - group and channel allocation
mt93l00a data sheet 16 zarlink semiconductor inc. figure 9 - memory mapping power up sequence on power up, the reset pin must be held low for 100 s. forcing the reset pin low will put the mt93l00 in power down state. in this state, all intern al clocks are halted, d< 7:0>, sout, rout, dta and irq pins are tristated. the 16 main control registers, the interrupt fifo register and the test regi ster are reset to zero. when the reset pin returns to logic high and a valid mclk is applied, the user must wait 500 s for the pll to lock. c4i and f0i can be active during this period. at this point, the echo canceller must have the internal registers reset to an initial state. this is accomplished by one of two methods. the user can either issue a second hardware reset or perform a software reset. a second har dware reset is performed by driving the reset pin low for at least 500 ns and no more than 1500 ns before being released. a software reset is accomplished by programming a ?1? to each of the pwup bits in the main control registers, waiting 250 s (2 frames) and then programming a ?0? to each of the pwup bits. the user must then wait 500 s for the pll to relock. once the pll has locked, the user can power up the 16 groups of echo cancellers individually by writing a ?1? into the pwup bit in main control register of each echo canceller group. for each group of echo cancellers, when the pwup bit toggles from zero to one, echo cancellers a and b execute their initialization routine. the initialization routine sets their regi sters, base address+00 h to base address+3f h , to the default reset value and clears the adaptive filter coefficients. two fr ames are necessary for the initialization routine to execute properly. once the initialization routine is executed, the user c an set the per channel control registers, base address+00 h to base address+3f h , for the specific application. 0000h --> channel 0, ec a ctrl/stat registers 001fh 0020h --> channel 1, ec b ctrl/stat registers 003fh 0040h --> channel 2, ec a ctrl/stat registers 005fh 0060h --> channel 3, ec b ctrl/stat registers 007fh 03c0h --> channel 30, ec a ctrl/stat registers 03dfh 03e0h --> channel 31, ec b ctrl/stat registers 03ffh 0400h --> 040fh main control registers <15:0> group 0 echo cancellers registers groups 2 --> 14 echo cancellers registers group 1 echo cancellers registers group 15 echo cancellers registers 0410h interrupt fifo register 0411h test register
mt93l00a data sheet 17 zarlink semiconductor inc. figure 10 - power up sequence flow diagram power management each group of echo cancellers can be placed in power down mode by writing a ?0? into the pwup bit in their respective main control register. when a given group is in power down mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. refer to the main control register section for description. the typical power consumption can be ca lculated with the following equation: p c = 9 * nb_of_groups + 3.6, in mw where 0 nb_of_groups 16 call initialization to ensure fast initial convergence on a new call, it is import ant to clear the adaptive filt er. this is done by putting the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation. system powerup delay 100 s reset held low reset high mclk active delay 500 s reg. reset software hardware reset low delay 1000 ns reset high pwup to ?1? delay 250 s pwup to ?0? delay 500 s ecan ready
mt93l00a data sheet 18 zarlink semiconductor inc. interrupts the mt93l00 provides an interrupt pin (irq ) to indicate to the host processor when a g.164 or g.165 tone disable is detected and released. although the mt93l00 may be configured to react automatically to tone disable status on any input pcm voice channels, the user may want for the ex ternal host processor to respond to tone disable information in an appropriate, application specific manner. each echo canceller will generate an interrupt when a tone disable occurs and w ill generate another interrupt when a tone disable releases. upon receiving an irq , the host cpu should read the interrupt fifo register. this register is a fifo memory containing the channel number of the echo canceller that has generated the interrupt. all pending interrupts from any of the echo cancellers and their associated input chan nel number are stored in this fifo memory. the irq always returns high after a read access to the interrupt fifo register. the irq pin will toggle low for each pending interrupt. after the host cpu has received the channel number of the interrupt source, the corresponding per channel status register can be read from internal memory to de termine the cause of the interrupt (see figure 8 for address mapping of status register). the td bit indicates the presence of a tone disable. the mirq bit 5 in the main control register 0 masks inte rrupts from the mt93l00. to provide more flexibility, the mtdbi (bit 4) and mtdai (bit 3) bits in the main c ontrol register<15:0> allow t one disable to be masked or unmasked, from generating an interrupt on a per channel basis. refer to the registers description section. jtag support the mt93l00 jtag interface conforms to the boundary-scan standard i eee1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the opera tion of the boundary scan circuitry is controlled by an external test access port (tap) controller. jtag inputs are 3.3 v compliant only. test access port (tap) the tap provides access to many test functions of the mt 93l00. it consists of three input pins and one output pin. the following pins are found on the tap. ? test clock input (tck) the tck provides the clock for the test logic. the t ck does not interfere with any on-chip clock and thus remains independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrent with the operation of the device and without interfering with the on-chip logic. ? test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising e dge of the tck pulse. this pin is internally pulled to vdd1when it is not driven from an external source. ? test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to th e tms input. both registers are described in a subsequent section. the received input data is samp led at the rising edge of tck pulses. this pin is internally pulled to v dd1 when it is not driven from an external source.
mt93l00a data sheet 19 zarlink semiconductor inc. ? test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out to wards the tdo. the data from the tdo is clocked on the falling edge of the tck pulses. when no data is shift ed through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) this pin is used to reset the jtag scan structure. this pin is internally pulled to v ss . instruction register in accordance with the ieee 1149.1 standard, the mt93 l00 uses public instructions. the jtag interface contains a 3-bit instruction register. instructions are serially loaded into the instruct ion register from the tdi when the tap controller is in its shifted-ir state. subsequently, the in structions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, a nd to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. test data registers as specified in ieee 11 49.1, the mt93l00 jtag interface cont ains three test data registers: ? boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the mt93l00 core logic. ? bypass register the bypass register is a single stage shift regist er that provides a one-bit path from tdi tdo. ? device identification register the device identification register provides access to the following encoded information: device version number, part number and manufacturer's name.
mt93l00a data sheet 20 zarlink semiconductor inc. register descriptions bit name description 7 reset when high, the power-up initialization is executed which presets all register bits including this bit and clears th e adaptive filter coefficients. 6 injdis when high, the noise injection proces s is disabled. when low noise injection is enabled. 5 bbm when high the back to ba ck configuration is enabled. when low the normal configuration is enabled. note: do not enable extended-delay and bbm configurations at the same time. always set both bbm bits of the two echo cancellers (control register a1 and control register b1) of the same group to the same logic value to avoid conflict. 4 pad when high, 12 db of attenuation is inserted into the rin to rout path. when low the rin to rout path gain is 0 db. 3 bypass when high, sin data is by-passed to sout and rin data is by-passed to rout. the adaptive filter coefficients are set to zero and the filter adaptation is stopped. when low, output data on both sout and rout is a function of the echo canceller algorithm. 2 adpdis when high, echo canceller adaptatio n is disabled. the mt93l00 cancels echo. when low, the echo canceller dynamically adapts to the echo path characteristics. 1 0 or 1 bits marked as ?1? or ?0? are reserv ed bits and should be written as indicated. 0extdl or 0 when high, echo cancellers a and b of the same group are internally cascaded into one 128 ms echo canceller. when low, echo cancellers a and b of the same group operate independently. note: do not enable both extended-delay and bbm configurations at the same time. control register b1 bit 0 is a reserved bit and should be written ?0?. echo canceller a, control register a1 read/write address: 00 h + base address 0 adpdis bypass pad bbm injdis reset 76543210 extdl echo canceller b, control register b1 read/write address: 20 h + base address 1 adpdis bypass pad bbm injdis reset 76543210 0 reset value: 00 h . reset value: 02 h .
mt93l00a data sheet 21 zarlink semiconductor inc. bit name description 7 tdis when high, tone detection is disabled . when low, tone detection is enabled. when both echo cancellers a and b tdis bits are high, tone disable processors are disabled entirely and are put into power down mode. 6 phdis when high, the tone detectors will tr igger upon the presence of a 2100 hz tone regardless of the presence/abs ence of periodic phase reversals. when low, the tone detector s will trigger only upon the presence of a 2100 hz tone with periodic phase reversals. 5 nlpdis when high, the non-linear processor is disabled. when low, the non-linear processors functi on normally. useful for g.165 conformance testing. 4 autotd when high, the echo canceller puts itself in bypass mode when the tone detectors detect the presence of 2100 hz tone. see phdis for qualification of 2100 hz tones. when low, the echo canceller algorithm wi ll remain operational regardless of the state of the 2100 hz tone detectors. 3 nbdis when high, the narrow-band detector is disabled. when low, the narrow-band detector is enabled. 2 hpfdis when high, the offset nulling high pass filters are bypassed in the rin and sin paths. when low, the offset nulling filters are ac tive and will remove dc offsets on pcm input signals. 1 mutes when high, data on sout is muted to quiet code. when low, sout carries active code. 0 muter when high, data on rout is muted to quiet code. when low, rout carries active code. echo canceller a, control register a2 echo canceller b, control register b2 muter mutes hpfdis nbdis autotd nlpdis phdis tdis 76543210 reset value: 00 h . read/write address: 01 h + base address read/write address: 21 h + base address
mt93l00a data sheet 22 zarlink semiconductor inc. fd 7 fd 6 fd 5 fd 4 fd 2 fd 1 fd 3 power reset value 00h 76543210 echo canceller a, flat delay register (fd) read/write address: 04h + base address echo canceller b, flat delay register (fd) read/write address: 24h + base address fd 0 power reset value 00h 76543210 ns 7 ns 6 ns 5 ns 4 ns 2 ns 1 ns 0 ns 3 echo canceller a, decay step number register (ns) read/write address: 07h + base address echo canceller b, decay step number register (ns) read/write address: 27h + base address power reset value 04h 76543210 0 0 0 0 ssc 2 ssc 1 ssc 0 0 echo canceller a, decay step size control register (ssc) read/write address: 06h + base address echo canceller b, decay step size control register (ssc) read/write address: 26h + base address note: bits marked with ?0? are reserved bits and should be written ?0?. amplitude of mu time flat delay (fd 7-0 ) step size (ss) 1.0 2 -16 fir filter length (512 or 1024 taps) number of steps (ns 7-0 ) the exponential decay registers (decay step number and decay step size) and flat delay register allow the lms adaptation step - size (mu) to be programmed over the length of the fir filter. a programmable mu profile allows the performance of the echo canceller to be optimized for specific applications. for example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the mu profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. note that in the following register descriptions, one tap is equivalent to 125 s (64 ms/512 taps). fd 7-0 flat delay : this register defines the flat delay of the mu profile, (i.e., where the mu value is 2 -16 ). the delay is defined as fd 7-0 x 8 taps. for example; if fd 7-0 = 5, then mu=2 -16 for the first 40 taps of the echo canceller fir filter. the valid range of fd 7-0 is: 0 fd 7-0 64 in normal mode and 0 fd 7-0 128 in extended-delay mode. the default value of fd 7-0 is zero. ssc 2-0 decay step size control : this register controls the step size (ss) to be used during the exponential decay of mu. the decay rate is defined as a decrease of mu by a factor of 2 every ss taps of the fir filter, where ss = 4 x2 ssc2-0 . for example; if ssc 2-0 = 4, then mu is reduced by a factor of 2 every 64 taps of the fir filter. the default value of ssc 2-0 is 04h. ns 7-0 decay step number : this register defines the number of steps to be used for the decay of mu where each step has a period of ss taps (see ssc 2-0 ). the start of the exponential decay is defined as: filter length (512 or 1024) - [decay step number (ns 7-0 ) x step size (ss)] where ss = 4 x 2 ssc2-0 . for example, if ns 7-0 =4 and ssc 2-0 =4, then the exponential decay start value is 512 - [ns 7-0 x ss] = 512 - [4x (4x2 4 )] = 256 taps for a filter length of 512 taps.
mt93l00a data sheet 23 zarlink semiconductor inc. bit name description 7 res reserved bit. 6 td logic high indicates the presence of a 2100 hz tone. 5 dtdet logic high indicates the presence of a double-talk condition. 4 res reserved bit. 3 res reserved bit. 2 res reserved bit. 1 tdg tone detection status bit gated with the autotd bit. logic high indicates that autotd has been enabled and the tone detector has detected the presence of a 2100 hz tone. 0 nb logic high indicates the presence of a narrow-band signal on rin. bit name description 7-4 res reserved bits. must always be set to zero for normal operation. 3 ringclr when high, the instability detector is activated. when low, the instability detector is disabled 2 pathclr when high, the current echo channel estimate will be cleared and the echo canceller will enter fast convergence mode upon detection of a path change. when low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. note: this bit is ignored if pathdet is low. 1 pathdet when high, the path change detector is activated. when low, the path change detector is disabled. 0 res reserved bit. must always be set to zero for normal operation. echo canceller a, status register echo canceller b, status register nb tdg res res res dtdet td res 76543210 reset value: 00 h . read address: 02 h + base address read address: 22 h + base address echo canceller a, control register a3 echo canceller b, control register b3 res pathdet pathclr ringclr res res res res 765432 10 reset value: 0a h . read/write address: 08 h + base address read/write address: 28 h + base address
mt93l00a data sheet 24 zarlink semiconductor inc. bit name description 7 0 must be set to zero. 6-4 supdec these three bits control how long the echo canceller remains in a fast convergence state following a path change, reset or bypa ss operation. a value of zero will keep the echo canceller in fast convergence indefinitely. 3-0 res reserved bits. must always be set to zero for normal operation. echo canceller a, control register a4 echo canceller b, control register b4 res res res res sd 0 sd 1 sd 2 0 765432 10 reset value: 50 h . read/write address: 09 h + base address read/write address: 29 h + base address power reset value 74h 76543210 ns 7 ns 6 ns 5 ns 4 ns 2 ns 1 ns 0 ns 3 echo canceller a, noise scaling (ns) read/write address: 0ah + base address echo canceller b, noise scaling (ns) read/write address: 2ah + base address if the comfort noise level estimator is unable to correctly match the background noise level, this register can be used to scal e the comfort noise up or down. a neut ral value of 80h will prevent an y scaling. values less than 80h will scale the comfort noise le vel down. values greater than 80h will scale the comfort noise level up. scaling is done linearly, so to scale the comfort noise down by 1 db, a value of 72h would be used (-1 db = 89% of original level, 0.89 (dec) ? 80h = 72h). similarly, to scale up by 1 db, use a value of 8fh (1 db = 112% of original level, 1.12 (dec) ? 80h = 8fh). power reset value 0ch 76543210 ir 7 ir 6 ir 5 ir 4 ir 2 ir 1 ir 0 ir 3 echo canceller a, injection rate (ir) read/write address: 0bh + base address echo canceller b, injection rate (ir) read/write address: 2bh + base address the nlp ramps-in comfort noise during the initial background noise estimation stage. this register provides control over the ramp-in speed. higher values will increase the ramp-in speed.
mt93l00a data sheet 25 zarlink semiconductor inc. power reset value n/a 76543210 rp 15 rp 14 rp 13 rp 12 rp 10 rp 9 rp 8 rp 11 echo canceller a, rin peak detect register 2 (rp) read address: 0dh + base address echo canceller b, rin peak detect register 2 (rp) read address: 2dh + base address power reset value n/a 76543210 rp 7 rp 6 rp 5 rp 4 rp 2 rp 1 rp 0 rp 3 echo canceller a, rin peak detect register 1 (rp) read address: 0ch + base address echo canceller b, rin peak detect register 1 (rp) read address: 2ch + base address these peak detector registers allow the user to monitor the receive in signal (rin) peak signal level. the information is in 16 bit 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. power reset value n/a 76543210 sp 15 sp 14 sp 13 sp 12 sp 10 sp 9 sp 8 sp 11 echo canceller a, sin peak detect register 2 (sp) read address: 0fh + base address echo canceller b, sin peak detect register 2 (sp) read address: 2fh + base address power reset value n/a 76543210 sp 7 sp 6 sp 5 sp 4 sp 2 sp 1 sp 0 sp 3 echo canceller a, sin peak detect register 1 (sp) read address: 0eh + base address echo canceller b, sin peak detect register 1 (sp) read address: 2eh + base address these peak detector registers allow the user to monitor the send in signal (sin) peak signal level. the information is in 16 bi t 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. power reset value n/a 76543210 ep 15 ep 14 ep 13 ep 12 ep 10 ep 9 ep 8 ep 11 echo canceller a, error p eak detect register 2 (ep) read address: 11h + base address echo canceller b, error p eak detect register 2 (ep) read address: 31h + base address power reset value n/a 76543210 ep 7 ep 6 ep 5 ep 4 ep 2 ep 1 ep 0 ep 3 echo canceller a, error p eak detect register 1 (ep) read address: 10h + base address echo canceller b, error p eak detect register 1 (ep) read address: 30h + base address these peak detector registers allow the user to monitor the error signal peak level. the information is in 16 bit 2?s complemen t linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte i s in register 1.
mt93l00a data sheet 26 zarlink semiconductor inc. power reset value 48h 7654 3210 dtdt 15 dtdt 14 dtdt 13 dtdt 12 dtdt 10 dtdt 9 dtdt 8 dtdt 11 echo canceller a, double-talk detection threshold register 2 read/write address: 15h + base address echo canceller b, double-talk detection threshold register 2 read/write address: 35h + base address power reset value 00h 7 6543 21 0 dtdt 7 dtdt 6 dtdt 5 dtdt 4 dtdt 2 dtdt 1 dtdt 0 dtdt 3 echo canceller a, double-talk detection threshold register 1 read/write address: 14h + base address echo canceller b, double-talk detection threshold register 1 read/write address: 34h + base address this register allows the user to program the level of double-talk detection threshold (dtdt). the 16 bit 2?s complement linear value defaults to 4800h= 0.5625 or -5 db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. (dtdt) (dtdt) power reset value 0bh 76543210 nlp 15 nlp 14 nlp 13 nlp 12 nlp 10 nlp 9 nlp 8 nlp 11 echo canceller a, non-linear processor threshold register 2 read/write address: 19h + base address echo canceller b, non-linear processor threshold register 2 read/write address: 39h + base address power reset value 60h 76543210 nlp 7 nlp 6 nlp 5 nlp 4 nlp 2 nlp 1 nlp 0 nlp 3 echo canceller a, non-linear processor threshold register 1 read/write address: 18h + base address echo canceller b, non-linear processor threshold register 1 read/write address: 38h + base address this register allows the user to program the level of the non-linear processor threshold (nlpthr). the 16 bit 2?s complement linear value defaults to 0b60h = 0.0889 or -21.0 db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. (nlpthr) (nlpthr) power reset value 40h 76543210 mu 15 mu 14 mu 13 mu 12 mu 10 mu 9 mu 8 mu 11 echo canceller a, adaptation step size (mu) register 2 read/write address: 1bh + base address echo canceller b, adaptation step size (mu) register 2 read/write address: 3bh + base address power reset value 00h 76543210 mu 7 mu 6 mu 5 mu 4 mu 2 mu 1 mu 0 mu 3 echo canceller a, adaptation step size (mu) register 1 read/write address: 1ah + base address echo canceller b, adaptation step size (mu) register 1 read/write address: 3ah + base address this register allows the user to program the level of mu. mu is a 16 bit 2?s complement value which defaults to 4000h = 1.0 the maximum value is 7fffh or 1.9999 decimal. the high byte is in register 2 and the low byte is in register 1. (mu) (mu)
mt93l00a data sheet 27 zarlink semiconductor inc. bit name description 7 wr_all write all control bit: when high, group 0-15 echo c ancellers registers are mapped into 0000h to 0003fh which is group 0 address mapping. useful to initialize the 16 groups of echo cancellers as per group 0. when low, address mapping is per figure 9. note: only the main control register 0 has the wr_all bit. 6 ode output data enable: this control bit is logically and?d with the ode input pin. when both ode bit and ode input pin are high, the rout and sout outputs are enabled. when the ode bit is low or the ode input pi n is low, the rout and sout outputs are high impedance . note: only the main control register 0 has the ode bit. 5 mirq mask interrupt: when high, all the interrupts from t he tone detectors output are masked. the tone detectors operate as specif ied in their echo canceller b, control register 2. when low, the tone detectors interrupts are active. note: only the main control register 0 has the mirq bit. 4 mtdbi mask tone detector b interrupt: when hi gh, the tone detector in terrupt output from echo canceller b is masked. the tone detector operates as specified in echo canceller b, control register 2. when low, the tone detector b interrupt is active. 3 mtdai mask tone detector a interrupt: when hi gh, the tone detector in terrupt output from echo canceller a is masked. the tone detector operates as specified in echo canceller a, control register 2. when low, the tone detector a interrupt is active. 2 format itu-t/sign mag: when high, both echo cancellers a and b for a given group, accept itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, accept sign-magnitude pcm code . 1lawa/ law: when high, both echo cancellers a and b for a given group, accept a-law companded pcm code. when low, both echo cancellers a and b for a given group, accept -law companded pcm code. main control register 0 (ec group 0) read/write address: 400 h pwup law format mtdai mtdbi mirq ode wr_all 76543210 reset value: 00 h .
mt93l00a data sheet 28 zarlink semiconductor inc. 0 pwup power-up: when high, both echo cancelle rs a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo canceller a and b execute their initialization routine which presets their registers, base address+00h to base address+3fh, to default reset value and clears the adaptive filter coefficients. two frames are necessary for the initializat ion routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers for their specific application. bit name description main control register 0 (ec group 0) read/write address: 400 h pwup law format mtdai mtdbi mirq ode wr_all 76543210 reset value: 00 h .
mt93l00a data sheet 29 zarlink semiconductor inc. bit name description 7-5 unused unused bits. 4 mtdbi mask tone detector b interrupt: when hi gh, the tone detector in terrupt output from echo canceller b is masked. the tone detector operates as specified in echo canceller b, control register 2. when low, the tone detector b interrupt is active. 3 mtdai mask tone detector a interrupt: when hi gh, the tone detector in terrupt output from echo canceller a is masked. the tone detector operates as specified in echo canceller a, control register 2. when low, the tone detector a interrupt is active. 2 format itu-t/sign mag: when high, both echo cancellers a and b for a given group, select itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, select sign-magnitude pcm code . 1lawa/ law: when high, both echo cancellers a and b for a given group, select a-law companded pcm code. when low, both echo cancellers a and b for a given group, select m-law companded pcm code . pwup law format mtdai mtdbi unused unused unused 76543210 reset value: 00 h . main control register 1 (ec group 1) read/write address: 401 h main control register 2 (ec group 2) read/write address: 402 h main control register 3 (ec group 3) read/write address: 403 h main control register 4 (ec group 4) read/write address: 404 h main control register 5 (ec group 5) read/write address: 405 h main control register 6 (ec group 6) read/write address: 406 h main control register 7 (ec group 7) read/write address: 407 h main control register 8 (ec group 8) read/write address: 408 h main control register 9 (ec group 9) read/write address: 409 h main control register 10 (ec group 10) read/write address: 40a h main control register 11 (ec group 11) read/write address: 40b h main control register 12 (ec group 12) read/write address: 40c h main control register 13 (ec group 13) read/write address: 40d h main control register 14 (ec group 14) read/write address: 40e h main control register 15 (ec group 15) read/write address: 40f h
mt93l00a data sheet 30 zarlink semiconductor inc. 0 pwup power-up: when high, both echo cancelle rs a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo cancellers a and b execute their initialization routine which presets t heir registers, base address+00h to base address+3fh, to default reset value and clears the adaptive filter coefficients. two frames are necessary for the initializat ion routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers for their specific application. bit name description pwup law format mtdai mtdbi unused unused unused 76543210 reset value: 00 h . main control register 1 (ec group 1) read/write address: 401 h main control register 2 (ec group 2) read/write address: 402 h main control register 3 (ec group 3) read/write address: 403 h main control register 4 (ec group 4) read/write address: 404 h main control register 5 (ec group 5) read/write address: 405 h main control register 6 (ec group 6) read/write address: 406 h main control register 7 (ec group 7) read/write address: 407 h main control register 8 (ec group 8) read/write address: 408 h main control register 9 (ec group 9) read/write address: 409 h main control register 10 (ec group 10) read/write address: 40a h main control register 11 (ec group 11) read/write address: 40b h main control register 12 (ec group 12) read/write address: 40c h main control register 13 (ec group 13) read/write address: 40d h main control register 14 (ec group 14) read/write address: 40e h main control register 15 (ec group 15) read/write address: 40f h
mt93l00a data sheet 31 zarlink semiconductor inc. bit name description 7 irq logic high indicates an interrupt has occu rred. irq bit is clear ed after the interrupt fifo register is read. logic low indicates that no interrupt is pending and the fifo is empty. 6:5 0 unused bits. always zero 4:0 i<4:0> i<4:0> binary code indicates the channel number at which a tone detector state change has occurred. note: whenever a tone disable is detect ed or released, an interrupt is generated. bit name description 7:1 res reserved bits. must always be set to zero for normal operation. 0 tirq test irq: useful for the application engineer to verify the interrupt service routine. when high, any change to mtdbi and mtdai bi ts of the main control register will cause an interrupt and its corresponding channel number will be available from the interrupt fifo register. when low, normal operation is selected. interrupt fifo register i0 i1 i2 i3 i4 0 0 irq 76543210 reset value: 00 h . read address: 410 h (read only) test register tirq res res res res res res res 76543210 reset value: 00 h . read/write address: 411 h
mt93l00a data sheet 32 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd1 =3.3 v and are for design aid only: not guaranteed and not subject to production testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage (v dd1 )v dd_io -0.5 5.0 v 2 core supply voltage (v dd2 )v dd_core -0.5 2.5 v 3 input voltage v i3 v ss - 0.5 v dd1 +0.5 v 4 input voltage on any 5 v tolerant i/o pins v i5 v ss - 0.3 7.0 v 5 continuous current at digital outputs i o 20 ma 6 package power dissipation p d 2w 7 storage temperature t s -55 150 c characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 +85 c 2 i/o supply voltage (v dd_io )v dd1 3.0 3.3 3.6 v 3 core supply voltage (v dd_core )v dd2 1.7 1.8 1.9 v 4 input high voltage on 3.3 v tolerant i/o v ih3 0.7v dd1 v dd1 v 5 input high voltage on 5 v tolerant i/o pins v ih5 0.7v dd1 5.5 v 6 input low voltage v il 0.3v dd1 v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 i n p u t s static supply current i cc 250 a reset = 0 idd_io (v dd 1 = 3.3 v) i dd_io 10 ma all 32 channels active idd_core (v dd 2 = 1.8 v) i dd_core 65 ma all 32 channels active 2 power consumption p c 150 mw all 32 channels active 3 input high voltage v ih 0.7v dd1 v 4 input low voltage v il 0.3v dd1 v 5 input leakage input leakage on pullup input leakage on pulldown i ih /i il i lu i ld -30 30 10 -55 65 a a a v in =v ss to v dd1 or 5.5 v v in =v ss v in =v dd1 see note 1 6 input pin capacitance c i 10 pf 7 o u t p u t s output high voltage v oh 0.8v dd1 vi oh = 12 ma 8 output low voltage v ol 0.4 v i ol = 12 ma 9 high impedance leakage i oz 10 av in =v ss to 5.5 v 10 output pin capacitance c o 10 pf
mt93l00a data sheet 33 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. i ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing. * note1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - timing parameter measurement voltage levels - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. level units conditions 1 cmos threshold v tt 0.5v dd1 v 2 cmos rise/fall threshold voltage high v hm 0.7v dd1 v 3 cmos rise/fall threshold voltage low v lm 0.3v dd1 v ac electrical characteristics ? - frame pulse and c4i characteristic sym. min. typ. ? max. units notes 1 frame pulse width (st-bus, gci) t fpw 20 2* t cp -20 ns 2 frame pulse setup time before c4i falling (st-bus or gci) t fps 10 122 150 ns 3 frame pulse hold time from c4i falling (st-bus or gci) t fph 10 122 150 ns 4c4i period t cp 190 244.1 300 ns 5c4i pulse width high t ch 85 150 ns 6c4i pulse width low t cl 85 150 ns 7c4i rise/fall time t r , t f 10 ns ac electrical characteristics ? - serial streams for st -bus and gci backplanes characteristic sym. min. typ. ? max. units test conditions 1 rin/sin set-up time t sis 10 ns 2 rin/sin hold time t sih 10 ns 3 rout/sout delay - active to active t sod 60 ns c l =150 pf 4 output data enable (ode) delay t ode 30 ns c l =150 pf, r l =1 k see note 1
mt93l00a data sheet 34 zarlink semiconductor inc. figure 11 - st-bus timing at 2.048 mbps figure 12 - gci interface timing at 2.048 mbps figure 13 - output driver enable (ode) v tt v tt f0i c4i t fpw rout/sout rin/sin t fph t sod t sih t ch t cl bit 0, channel 31 t fps t cp t sis v tt v tt bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 bit 0, channel 31 bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 v hm v lm t r t f v tt v tt f0i c4i t fpw sout/rout sin/rin t fph t sod t sih t ch t cl bit 7, channel 31) t fps t cp t sis v tt v tt bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 bit 7, channel 31) bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 t r t f v hm v lm v tt hiz hiz sout/rout ode t ode t ode valid data v tt
mt93l00a data sheet 35 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing. figure 14 - master clock ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing. * note 1: high impedance is measured by pulling to the appro priate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - master clock - voltages are with respect to ground (v ss ). unless otherwise stated. characteristic sym. min. typ. ? max. units notes 1 master clock frequency, - fsel = 0 - fsel = 1 f mcf0 f mcf1 19.0 9.5 20.0 10.0 21.0 10.5 mhz mhz 2 master clock low t mcl 20 ns 3 master clock high t mch 20 ns ac electrical characteristics ? - motorola non-multiplexed bus mode characteristics sym. min. typ. ? max. units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 0ns 3 address setup from ds falling t ads 0ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 0ns 6 address hold after ds rising t adh 0ns 7 data delay on read t ddr 79 ns c l =150 pf, r l =1 k 8 data hold on read t dhr 315nsc l =150 pf, r l =1 k see note 1 9 data setup on write t dsw 0ns 10 data hold on write t dhw 0ns 11 acknowledgment delay t akd 80 ns c l =150 pf, r l =1 k 12 acknowledgment hold time t akh 08nsc l =150 pf, r l =1 k, see note 1 13 irq delay t ird 20 65 ns c l =150 pf, r l =1 k, see note 1 t mch t mcl v tt mclk
mt93l00a data sheet 36 zarlink semiconductor inc. figure 15 - motorola non-multiplexed bus timing ds a0-a10 cs d0-d7 d0-d7 read write t css t csh t adh t dhr t rws r/w t ads t rwh t dhw t akd t dsw t ddr t akh dta v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data t ird irq v tt

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